This invention relates to circuitry useful, for example, in digital transmission systems for recovering the clock from an incoming non-return-to-zero (NRZ) digital data stream. Such data streams will have transition densities which vary with the intelligence being transmitted and also with the statistically varying scrambling pattern applied to the intelligence signal at the transmitter. A transition is a change in voltage level of the data stream when the signal changes binary state, and transition density is the number of transitions as a percentage of the total number of time slots. Strings of binary 1s or 0s will produce no voltage changes or transitions. Most phase and frequency detectors which are parts of phase locked loops depend on the periodic nature of the incoming signal to provide information about its frequency and phase. The aforementioned NRZ signals with varying transition density do not have this regularly recurring or periodic feature, which would facilitate the extraction of the phase and frequency information therefrom. For this reason specialized circuitry must be utilized for phase/frequency locked loops used with NRZ signals.
A phase locked loop is a circuit for locking the phase of a local voltage controlled oscillator (VCO) with an input signal which may be varying in frequency and/or phase and may contain noise. Phase locked loops may be used as demodulators for phase shift keyed binary signals or they may be used to track a phase or frequency varying input, for example, to recover the clock of an incoming digital data signal. When used to track a carrier signal the phase locked loop may be thought of as a narrow band filter for removing noise and thus generating a clean replica of the carrier. A simple phase locked loop comprises a phase detector to which the input signal and the output of a VCO are applied, with the phase detector output applied to the frequency control element of the VCO via a low pass filter. The hold-in range of such a circuit is the maximum change in input frequency for which the loop will remain locked. This is governed by the dc gain of the loop and the frequency control range of the VCO. As the input frequency changes, the phase error will continually increase until the loop unlocks and the phase detector produces an ac beat note output. The pull-in range is the range of frequencies which the loop will lock to if it is initially unlocked. If the two frequencies applied to the phase detector are close enough, the feedback loop will contain a dc component which will cause the VCO to move toward frequency and phase lock. The loop bandwidth is the range of frequencies of phase jitter which will pass through the loop with relatively little attenuation. A narrow loop bandwidth is required to reduce phase jitter in the VCO output, but this severely restricts the pull-in range. Prior art methods used to achieve phase lock or acquisition have included compromises in loop filter design, highly accurate VCOs, sweeping VCOs and loop filters which can be switched from wide to narrow bandwidth after phase lock has been achieved. An example of this latter method is the circuit of U.S. Pat. No. 4,200,845, issued to Mendenhall et al. on Apr. 29, 1980. Another technique is to use a frequency detector in addition to the phase detector, wherein the frequency detector generates a frequency error signal proportional to the frequency difference between the input and VCO frequencies, and this error signal drives the VCO toward the input frequency. When the frequency error is small, the phase detector will start to generate a dc phase error signal which produces and maintains phase lock. With this circuitry, the loop bandwidth can be small and the pull-in range large.
The prior art includes digital phase/frequency locked loops wherein separate frequency and phase detectors jointly control the VCO, as explained above, however, most of these prior art circuits are not designed to function with input NRZ signals of the types described above; such circuits require a periodic input signal with regularly recurrent transitions. Examples of such prior art digital phase/frequency locked loops are shown in U.S. Pat. Nos. 3,714,463 issued to Laune on Jan. 30, 1973 and 4,594,564 issued to Yarborough on June 10, 1986.
The present invention is useful as part of synchronizing circuitry for digital transmission systems wherein numerous digital channels are required to be phase synchronized (or aligned) with a locally generated master clock at a terminal or repeater. The different channels and the local clock will all have the same long term synchronous frequency but the incoming channels may have randomly varying phases caused, for example, by the traversal of different transmission media with different propagational velocities and/or different distances. Also, upon switch-on or following a supply voltage surge, the VCO may be temporarily out of phase lock and may therefore require frequency correction. The synchronization of such channels facilitates the synchronous processing of these signals, since all of the terminal or repeater processing circuitry can operate from a single master clock to which all incoming signals have been synchronized.
In my co-pending application entitled "Digital Phase Aligner", Ser. No. 946,323, filed on Dec. 24, 1986, which issued on Jul. 5, 1988, as U.S. Pat. No. 4,756,011, novel circuitry is disclosed and claimed for achieving such synchronization or phase alignment by sampling each of the incoming data streams at four points (0.degree., 90.degree., 180.degree., and 270.degree.) of the local clock and wherein the in-phase (0.degree.)and anti-phase (180.degree.) samples are loaded into different halves of a bi-phase register, which is clocked by the local clock. As the data stream and local clock vary in phase, a logic circuit detects such phase variations by logic analysis of the aforementioned four samples and in response thereto automatically selects one of the stages of the bi-phase register for connection to the output, so that no data is lost. The output is thus a delayed replica of the input data stream but at the bit rate of the local clock.
A different known technique for achieving phase alignment of such phase-varying synchronous digital data streams involves the use of a FIFO (first-in, first-out) register wherein the incoming data stream is clocked into one end of the FIFO and the locally generated master clock is used to clock the data out of the other end thereof. Phase variations between the incoming data stream and the local master clock will cause the FIFO to fill up or become depleted, but the system is designed so that the FIFO is never fully depleted and never overflows. In such a system, if the incoming data does not have a clock signal, which is the usual case, it is necessary to recover the incoming clock of each channel from the data stream thereof with a phase/frequency locked loop. The recovered clock is then used to clock the data into the FIFO. The circuit of the present invention is such a phase/frequency locked loop.